GeoByJmh - Embedded Engineer: Pacemaker

Showing posts with label Pacemaker. Show all posts

Showing posts with label Pacemaker. Show all posts

Sunday, 9 September 2012

Pacemaker Finished

I have just finished the Doulos (http://www.doulos.com) VHDL Tutorial called Pacemaker. The notes I made while working through the tutorial can be found in this blog and cover:

VHDL State Encoding

type StateType is
(Idle, Start, Stop, Clear);
signal State: StateType;

The states will be encoded as below. We can change the encoding by changing the order in the type statement.
Idle = 00
Start = 01
Stop = 01
Clear = 11

However some synthesis tools can be told to optimize the SM automatically. Do not turn on this option if you want to be in full control.

----
Unreachable states are created with the following type def.

type StateType is
(One, Two, Three, Four, Five);

This is ok but if you want to specify what happens specify the dummy states you can create this as follows:

type StateType is
(One, Two, Three, Four, Five,
Dummy1, Dummy2, Dummy3);

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial. Any content copied from the tutorial has been reproduced with permission. http://www.doulos.com.

VHDL No Output Decoding Logic

architecture NoDecoding of AnotherFSM is
constant Idle: STD_LOGIC_VECTOR := "11";
constant Start: STD_LOGIC_VECTOR := "01";
constant Stop: STD_LOGIC_VECTOR := "10";
constant Clear: STD_LOGIC_VECTOR := "00";
signal State: STD_LOGIC_VECTOR(1 downto 0);
begin
process
begin
wait until RISING_EDGE(Clock);
if Reset = '0' then State <= Idle;
else
case State is
when Idle => State <= Start;
when Start => State <= Stop;
when Stop => State <= Clear;
when Clear => State <= Idle;
when others => State <= Idle;
end case;
end if;
end process;
P <= State(1);
Q <= State(0);
end;

In the above example we have coded the states.
The output is just a reference to the states.

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial. Any content copied from the tutorial has been reproduced with permission. http://www.doulos.com.

VHDL SM Separating Registers

architecture RegistersPlusLogic of FSM is
type StateType is (Idle, Start, Stop, Clear);
signal State: StateType;
begin
Registers: process
begin
wait until RISING_EDGE(Clock);
if Reset = '0' then
State <= Idle;
else
State <= NextState;
end if;
end process;

C_logic: process (State)
begin
if State = Clear then NextState <= Idle;
F <= '1';
elsif State = Idle then NextState <= Start;
G <= '1';
elsif State = Start then NextState <= Stop;
else NextState <= Clear;
end if;

end process;
end;

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial. Any content copied from the tutorial has been reproduced with permission. http://www.doulos.com.

Explicit State Machine

architecture Explicit of FSM is
begin
process
type StateType is (Idle, Start, Stop, Clear);
variable State: StateType;
begin
wait until RISING_EDGE(Clock);
if Reset = '1' then
State := Idle; F <= '0'; G <= '1';
else
case State is
when Idle => State := Start; G <= '0';
when Start => State := Stop;
when Stop => State := Clear; F <= '1';
when Clear => State := Idle; F <= '0';
G <= '1';
end case;
end if;
end process;
end;

To avoid the outputs being registered we must split the VHDL into two processes.

architecture SeparateDecoding of FSM is
type StateType is (Idle, Start, Stop, Clear);
signal State: StateType;
begin
Change_state: process
begin
wait until RISING_EDGE(Clock);
if State = Clear or Reset = '1' then
State <= Idle;
elsif State = Idle then State <= Start;
elsif State = Start then State <= Stop;
else State <= Clear;
end if;
end process;

Output: process (State)
begin
F <= '0'; G <= '0';
if State = Clear then F <= '1';
elsif State = Idle then G <= '1';
end if;
end process;

end;

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial. Any content copied from the tutorial has been reproduced with permission. http://www.doulos.com.

VHDL Variables & Registers

signal Reg: STD_LOGIC;
...

AND_REG: process
variable V: STD_LOGIC; -- V is a wire.
begin
wait until RISING_EDGE(Clock);
V := '1';
for I in 0 to 7 loop
V := V and Input(I);
end loop;
Reg <= V; -- Reg is a FF
end process;

Reg is a signal so will always become a register.
V is assigned to 1 at the top of the file. We do not have to store the value of V between clock cycles so V is a wire.

---

Counter: process
variable Count:
STD_LOGIC_VECTOR(7 downto 0);
begin
wait until RISING_EDGE(Clock);
if Reset = '0' then
Count := "00000000"; -- Count is a 8 FF's
else
Count := Count + '1';
end if;
Output <= Count(7); -- Output is one FF. However some Synthis tools will merge this out.
end process;

---

process
begin
wait until RISING_EDGE(Clock);
Q <= Data;
QB <= not Data;
end process;

The above will create two flip flops. This is corrected below.

process
begin
wait until RISING_EDGE(Clock);
Q <= Data;
end process;

QB <= not Q;

--

Note is we want to describe a shift register using a variable we need to move from the out

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial. Any content copied from the tutorial has been reproduced with permission. http://www.doulos.com.

Saturday, 8 September 2012

VHDL The Five Process Styles

Style 1: Pure combinational logic

T1: process (All_Inputs)
begin
... Pure combinational logic
end process;

Rule: Complete sensitivity list
Rule: All outputs completely assigned
Rule: No feedback.

---
Style 2: Transparent Latch

T2: process (All_Inputs)
begin
if Enable = '1' then
... Transparent latches + logic
end if;
end process;

The transparent latch has:

Rule: a single if statement with not else.
Rule: Complete sensitivity list
Rule: No feedback.

---
Style 3: FF Using IF

T3: process (Clock)
begin
if RISING_EDGE(Clock) then
... Flipflops + logic
end if;
end process;

Rule: The assignments must be syncronised to the clock edge
Rule: The must not be an ELSE statement
Rule: Check tool support of RISING_EDGE
Rule: No statements must be placed after the END IF

--
Style 4: FF Using Wait

T4: process
begin
wait until RISING_EDGE(Clock);
... Flipflops + logic
end process;

Rule: The assignments must be syncronised to the clock edge
Rule: Check tool support of RISING_EDGE

--
Style 5: FF with Asynchronous Inputs

T5: process (Clock, Reset)
begin
if Reset = '0' then
... Asynchronous actions
elsif RISING_EDGE(Clock) then
... Flipflops + logic
end if;
end process;

Rule: All asynchronous inputs must me added to the sensitivity list
Rule: You must check their value first before the clock check.
Rule: The assignments must be syncronised to the clock edge
Rule: The must not be an ELSE statement
Rule: Check tool support of RISING_EDGE
Rule: No statements must be placed after the END IF

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial. Any content copied from the tutorial has been reproduced with permission. http://www.doulos.com.

VHDL FF using Wait Unitil

Another_Flipflop: process
begin

wait until Clock = '1'; -- must be the first statement in the process

if Reset = '1' then
Q <= '0';
else
Q <= D;
end if;

end process;

The process will run until it reaches the wait statement. then we assume the process is suspended until we get a rising clock.

---

Another_Flipflop: process
begin
wait until RISING_EDGE(Clock);

if Reset = '1' then
Q <= '0';
else
Q <= D;
end if;
end process;

We could use the rising_edge in the wait statement to create a clock.

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial. Any content copied from the tutorial has been reproduced with permission. http://www.doulos.com.

Flip Flop with Enable

process (Clock)
begin
if RISING_EDGE(Clock) then

if Reset = '1' then
Q <= '0';

elsif Enable = '1' then
Q <= Data;
end if;

end if;
end process;

Depending on the technology the enable will either make use of the specific feature of an FPGA or will be implemented using a multiplexer.

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial. Any content copied from the tutorial has been reproduced with permission. http://www.doulos.com.

VHDL Technology Dependent Components

architecture A1 of Block1 is
...
component GlobalResetBuffer
port (Pin: in Std_logic);
end component;

signal Reset: Std_logic;
begin

G: GlobalResetBuffer
port map (Reset);

process (Clock, Reset)
begin
if Reset = '0' then
Q <= '0';
elsif RISING_EDGE(Clock) then
Q <= Data;
end if;
end process;
...

Sometime we need to use specific areas of the FPGA. We can do this in VHDL for example we have specified a global reset above. However the VHDL will no longer be vendor independent.

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial. Any content copied from the tutorial has been reproduced with permission. http://www.doulos.com.

VHDL Asynchronous FF Reset

process (Clock, Reset)
begin

if Reset = '0' then
Count <= "00000000";

elsif RISING_EDGE(Clock) then

if Load = '1' then
Count <= Data;
else
Count <= Count + '1';
end if;

end if;

end process;

This example show a flip flop with asynchronous reset.

---

...
signal Count :
STD_LOGIC_VECTOR(7 downto 0);
begin
process (Clock, Reset)
begin
if Reset = '0' then
Count <= "00000000";
elsif RISING_EDGE(Clock) then
if Load = '1' then
Count <= Data; --load the counter
else
Count <= Count + '1'; -- increment the counter
end if;
end if;
end process;

Asynchronous and Synchronous parts of a eight bit counter with synchronous load.

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial. Any content copied from the tutorial has been reproduced with permission. http://www.doulos.com.

Thursday, 6 September 2012

VHDL Edge Triggered Flip Flop

process (Clock)
begin

if Clock'EVENT and Clock = '1' then

Q0 <= D0;
Q1 <= D1;

end if;

end process;

The tick event attribute is used to create a latch controlled by a clock. The Clock'EVENT will infer a flip flop.

We could use a function in the 1164 packge to look at clock edges.

library IEEE;
use IEEE.STD_LOGIC_1164.all;

...

process (Clock)
begin

if RISING_EDGE(Clock) then
Q <= D;
end if;

end process;

---

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial. Any content copied from the tutorial has been reproduced with permission. http://www.doulos.com.

VHDL Transparent Latch

process (ENB, D)
begin
if ENB = '1' then
Q <= D;
end if;
end process;

The value of Q will only change to Q if ENB is high. This is know as an incomplete assignment. Latch should no be used in FPGA because they need asynchronous feedback.

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial. Any content copied from the tutorial has been reproduced with permission. http://www.doulos.com.

VHDL Conversion Functions

We could not be allowed to assign and integer to a binary value. But we can use a conversion function such as To_unsigned to allow us to achieve this.

use IEEE.NUMERIC_STD.all;

...

signal A: Unsigned(7 downto 0);
signal F: Unsigned(2 downto 0);

...

Priority_encoder: process (A)
begin
F <= "000";
for I in 0 to 7 loop
if A(I) = '1' then
F <= To_unsigned(I, 3);
exit;
end if;
end loop;
end process;

---
The example below is used to assign an integer to a type STD_LOGIC.

use IEEE.NUMERIC_STD.all;

...

signal A: Unsigned(7 downto 0);
signal S: Unsigned(2 downto 0);
signal G: Std_logic;

...

Mux: G <= A(To_integer(S));

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial. Any content copied from the tutorial has been reproduced with permission. http://www.doulos.com.

Synthesis if Arithmetic Operators

F <= A + B;

This will synthesis to either:
1 - Non-optimal connection of FPGA cells or
2- Optimized structure of FPGA cells.

Some thisis acn take a + or - and map it directly to a standard block. But sometimes we need to use a vendor specific component our self's:

C1: ADDER8 port map (A,B,F)

The implementation depends on speed or size needed i.e. ripple carry adder v carry look-ahead adder.

Resource sharing can happen if the operators are on different paths of the same if statement.

process (A, B, C, D, K)
begin
if K then
Z <= A + B; -- 8 Bit
else
Z <= C + D;
end if;
end process;

Share the same adder block.

However if the synthesis tool does not support resource sharing then the code could be rewritten to force the resource to be shared.

process (A, B, C, D, K)
variable V1, V2 : ...
begin
if K then
V1 := A;
V2 := B;
else
V1 := C;
V2 := D;
end if;
Z <= V1 + V2;

end process;

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial. Any content copied from the tutorial has been reproduced with permission. http://www.doulos.com.

VHDL Operator Overloading

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;

entity ADDER is
port(A, B: in UNSIGNED(7 downto 0);
SUM: out UNSIGNED(7 downto 0));
end;

architecture A1 of ADDER is
begin
SUM <= A + B;
end;

The + and - can not be used with STD_LOGIC. We could use a vendor specific package that overloads these operators. However the IEEE.NUMERIC_STD package has created two new datatypes SIGNED and UNSIGNED. These do have overloaded operators for + and -.

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial. Any content copied from the tutorial has been reproduced with permission. http://www.doulos.com.

VHDL Std_Logic_Vector

signal
A, B: STD_LOGIC_VECTOR(7 downto 0);
signal
F: STD_LOGIC_VECTOR(15 downto 0);

F <= A & B; -- Concatenation

----

signal A, B, C: STD_LOGIC;
signal
F: STD_LOGIC_VECTOR(3 downto 0);

F(3 downto 1) <= (A & B) & C; -- concatenate bit.

---
Signal Reg: STD_LOGIC_VECTOR(7 downto0);
Reg <= Reg(6 downto 0) & '0'; -- shift
Reg <= Reg(6 downto 0) & Reg(7); -- rotate

---

Reg <= Reg sll '0'; -- shift VHDL 93 only
Reg <= Reg rol Reg(7); -- rotate VHDL 93 only

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial. Any content copied from the tutorial has been reproduced with permission. http://www.doulos.com.

Wednesday, 5 September 2012

VHDL Constant

constant Active: Std_logic := '0';
constant SIZE: INTEGER := 16;
constant ZERO: STD_LOGIC_VECTOR := "0000";

The value can not be changed.

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial. Any content copied from the tutorial has been reproduced with permission. http://www.doulos.com.

VHDL Logical Operators

AND
OR
NOT
NAND
NOR
XOR
XNOR

y <= a AND b;

The STD_LOGIC will synthesize to a single wire.

type STD_ULOGIC is (
'U', -- Value at time 0
'X',  - Strong - Unknown
'0', - Strong
'1',   - Strong   'Z', -- High impedance
'W', - Week, Pull up resistor. - Unknown
'L',  - Week, Pull up resistor. 'H',  - Week, Pull up resistor.

'-'); -- Don't care

case IP is
when "00" =>
OP <= "0--1"; -- don't care
when "01" =>
OP <= "1-0-";
when "10" =>
OP <= "--10";
when others =>
OP <= "101-";
end case;

---

type Opcode is (Add, Neg, Load,
Store, Jmp, Halt);

signal S: Opcode := Halt;

variable
V: Std_logic_vector(0 to 1) := "00";

initialize signals and variables using :=
Do not use initial values of synthesis. They are only used for simulation.

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial. Any content copied from the tutorial has been reproduced with permission. http://www.doulos.com.

VHDL Enumeration Types

type Opcode is (Add, Neg, Load,

Store, Jmp, Halt);

signal S: Opcode;

The names Add, Neg, Load, Store, Jmp, Halt do not represent any binary bit patterns.

---

architecture V1 of Ent is

type Opcode is (Add, Neg, Load,

Store, Jmp, Halt);

signal S: Opcode;

begin

C1: Reg port map (..., S, ...);

C2: Ctl port map (..., S, ...);

end;

The values will be encoded as a binary number 000,001,010,011 etc.

---

type BOOLEAN is (FALSE, TRUE); -- package standard

type BIT is ('0', '1'); -- package standard

type STD_ULOGIC is --- package standard logic

('U', 'X', '0', '1',

'Z', 'W', 'L', 'H', '-');

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial. Any content copied from the tutorial has been reproduced with permission. http://www.doulos.com.

Subscribe to: Posts (Atom)