VHDL FF using Wait Unitil

  Another_Flipflop: process
  begin

    wait until Clock = '1'; -- must be the first statement in the process

    if Reset = '1' then
      Q <= '0';
    else
      Q <= D;
    end if;

  end process;


The process will run until it reaches the wait statement. then we assume the process is suspended until we get a   rising clock.


---

  Another_Flipflop: process
  begin
    wait until RISING_EDGE(Clock);

    if Reset = '1' then
      Q <= '0';
    else
      Q <= D;
    end if;
  end process;


We could use the rising_edge in the wait statement to create a clock.

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial.   Any content copied from the tutorial has been reproduced with permission.  http://www.doulos.com.