VHDL Std_Logic_Vector

signal
    A, B: STD_LOGIC_VECTOR(7 downto 0);
signal
    F: STD_LOGIC_VECTOR(15 downto 0);

F <= A & B; -- Concatenation

----



signal A, B, C: STD_LOGIC;
signal
    F: STD_LOGIC_VECTOR(3 downto 0);

F(3 downto 1) <= (A & B) & C; -- concatenate bit.


---
Signal Reg: STD_LOGIC_VECTOR(7 downto0);
Reg <= Reg(6 downto 0) & '0'; -- shift
Reg <= Reg(6 downto 0) & Reg(7); -- rotate

---

Reg <= Reg  sll '0'; -- shift VHDL 93 only
Reg <= Reg rol Reg(7); -- rotate VHDL 93 only

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial.   Any content copied from the tutorial has been reproduced with permission.  http://www.doulos.com.