VHDL Operator Overloading

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;

entity ADDER is
  port(A, B: in UNSIGNED(7 downto 0);
       SUM: out UNSIGNED(7 downto 0));
end;

architecture A1 of ADDER is
begin
  SUM <= A + B;
end;


The + and - can not be used with STD_LOGIC. We could use a vendor specific package that overloads these operators. However the IEEE.NUMERIC_STD package has created two new datatypes SIGNED and UNSIGNED. These do have overloaded operators for + and -.

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial.   Any content copied from the tutorial has been reproduced with permission.  http://www.doulos.com.