VHDL No Output Decoding Logic

architecture NoDecoding of AnotherFSM is
  constant Idle:  STD_LOGIC_VECTOR := "11";
  constant Start: STD_LOGIC_VECTOR := "01";
  constant Stop:  STD_LOGIC_VECTOR := "10";
  constant Clear: STD_LOGIC_VECTOR := "00";
  signal   State: STD_LOGIC_VECTOR(1 downto 0);
begin
  process
  begin
    wait until RISING_EDGE(Clock);
    if Reset = '0' then State <= Idle;
    else
      case State is
        when Idle   => State <= Start;
        when Start  => State <= Stop;
        when Stop   => State <= Clear;
        when Clear  => State <= Idle;
        when others => State <= Idle;
      end case;
    end if;
  end process;
  P <= State(1);
  Q <= State(0);
end;


In the above example we have coded the states.
The output is just a reference to the states.

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial.   Any content copied from the tutorial has been reproduced with permission.  http://www.doulos.com.