VHDL Variables & Registers

signal Reg: STD_LOGIC;
...

AND_REG: process
  variable V: STD_LOGIC; -- V is a wire.
begin
  wait until RISING_EDGE(Clock);
  V := '1';
  for I in 0 to 7 loop
    V := V and Input(I);
  end loop;
  Reg <= V; -- Reg is a FF
end process;


Reg is a signal so will always become a register.
V is assigned to 1 at the top of the file. We do not have to store the value of V between clock cycles so V is a wire.

---


Counter: process
  variable Count:
          STD_LOGIC_VECTOR(7 downto 0);
begin
  wait until RISING_EDGE(Clock);
  if Reset = '0' then
    Count := "00000000"; -- Count is a 8 FF's
  else
    Count := Count + '1';
  end if;
  Output <= Count(7); -- Output is one  FF. However some Synthis tools will merge this out.
end process;


---



process
begin
  wait until RISING_EDGE(Clock);
  Q <= Data;
  QB <= not Data;
end process;

The above will create two flip flops. This is corrected below.


process
begin
  wait until RISING_EDGE(Clock);
  Q <= Data;
end process;

QB <= not Q;


--

Note is we want to describe a shift register using a variable we need to move from the out

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial.   Any content copied from the tutorial has been reproduced with permission.  http://www.doulos.com.