Explicit State Machine

architecture Explicit of FSM is
begin
  process
    type StateType is (Idle, Start, Stop, Clear);
    variable State: StateType;
  begin
    wait until RISING_EDGE(Clock);
    if Reset = '1' then
      State := Idle; F <= '0'; G <= '1';
    else
      case State is
        when Idle  => State := Start; G <= '0';
        when Start => State := Stop;
        when Stop  => State := Clear; F <= '1';
        when Clear => State := Idle;  F <= '0';
                                      G <= '1';
      end case;
    end if;
  end process;
end;


To avoid the outputs being registered we must split the VHDL into two processes.

 architecture SeparateDecoding of FSM is
  type StateType is (Idle, Start, Stop, Clear);
  signal State: StateType;
begin
  Change_state: process
  begin
    wait until RISING_EDGE(Clock);
    if    State = Clear or Reset = '1' then
                             State <= Idle;
    elsif State = Idle  then State <= Start;
    elsif State = Start then State <= Stop;
    else                     State <= Clear;
    end if;
  end process;

  Output: process (State)
  begin
    F <= '0'; G <= '0';
    if    State = Clear then F <= '1';
    elsif State = Idle  then G <= '1';
    end if;
  end process;

end;

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial.   Any content copied from the tutorial has been reproduced with permission.  http://www.doulos.com.