VHDL Test Bench

Note the entity for the test bench has no ports

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity TEST_MUX4 is
end;

Reference the component 

architecture BENCH of TEST_MUX4 is
  component MUX4
    port (SEL: in
          STD_LOGIC_VECTOR(1 downto 0);
          A, B, C, D: in STD_LOGIC;
          F: out STD_LOGIC);
  end component;
  ...
begin
  ...
end BENCH;

Instantiate the component 

architecture BENCH of TEST_MUX4 is
  ...
  signal SEL:
         STD_LOGIC_VECTOR(1 downto 0);
  signal A, B, C, D, F: STD_LOGIC;
begin
  ...
  M: MUX4 port map(SEL, A, B, C, D, F);
end BENCH;

Main test bench

architecture BENCH of TEST_MUX4 is
  ...
begin
  SEL <= "00", "01" after 30 NS,
  "10" after 60 NS, "11" after 90 NS,
  "XX" after 120 NS, "00" after 130 NS;
  A <= 'X',
       '0' after 10 NS,
       '1' after 20 NS;
  B <= 'X',
       '0' after 40 NS,
       '1' after 50 NS;
  C <= 'X',
       '0' after 70 NS,
       '1' after 80 NS;
  D <= 'X',
      '0' after 100 NS,
      '1' after 110 NS;
  ...
end BENCH;

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial.   Any content copied from the tutorial has been reproduced with permission.  http://www.doulos.com.

VHDL STD_LOGIC

signal B: STD_LOGIC;
...
B <= '0';
...
B <= '1';
...
B <= 'X';


signal V: STD_LOGIC_VECTOR(7 downto 0);

v <="1010xxxx";
v(7) <= v(6);
v(1) <='1';
W <= v(5 downto 3); -- Slice
v(5 downto 3) <="10xz"

---

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity MUX4 is
 port (
   SEL:in STD_LOGIC_VECTOR(1 downto 0);
   A, B, C, D: in STD_LOGIC;
   F: out STD_LOGIC);
end MUX4;

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial.   Any content copied from the tutorial has been reproduced with permission.  http://www.doulos.com.

VHDL Design Entity Referance

G1: entity WORK.INV(ARCH)
  port map (SEL, SELB);
G2: entity WORK.AOI(V2)
  port map (SEL, A, SELB, B, F);

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial.   Any content copied from the tutorial has been reproduced with permission.  http://www.doulos.com.

VHDL Component Declaration and Instantiation

architecture STRUCTURE of MUX2 is
  component INV
    port (A: in  STD_LOGIC;
          F: out STD_LOGIC);
  end component;
  component AOI
    port (A, B, C, D: in STD_LOGIC;
          F: out STD_LOGIC);
  end component;
  signal SELB: STD_LOGIC;
begin
  G1: INV port map(SEL, SELB);
  G2: AOI port map(SEL, A, SELB, B, F);
end STRUCTURE;

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial.   Any content copied from the tutorial has been reproduced with permission.  http://www.doulos.com.

VHDL Concurrent Signal Assignmants

architecture RTL of ENT is
  signal A1, A2, XX: STD_LOGIC;
begin
   A1 <= A and B after 2 NS;
   A2 <= X1 and X2 after 2 NS;
   XX <= A1 or A2 after 2NS
end RTL;

An event or change in value will trigger a concurrent signal assignment.  There is a delay (propagation delay) of 2 NS from an event to the signal changing.

It does not matter what order the signals are written.

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial.   Any content copied from the tutorial has been reproduced with permission.  http://www.doulos.com.

VHDL Signals

architecture RTL of ENT is
  signal A1, A2, XX: STD_LOGIC;
begin
  ...
end RTL;

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial.   Any content copied from the tutorial has been reproduced with permission.  http://www.doulos.com.

VHDL Design Entity

library ieee;
use ieee.std_logic_1164.all;

entity ent is
  port(a,b :in std_logic;
       z :out std_logic_vector(3 downto 0));
end ent;

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial.   Any content copied from the tutorial has been reproduced with permission.  http://www.doulos.com.