VHDL Test Bench

Note the entity for the test bench has no ports

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity TEST_MUX4 is
end;

Reference the component 

architecture BENCH of TEST_MUX4 is
  component MUX4
    port (SEL: in
          STD_LOGIC_VECTOR(1 downto 0);
          A, B, C, D: in STD_LOGIC;
          F: out STD_LOGIC);
  end component;
  ...
begin
  ...
end BENCH;

Instantiate the component 

architecture BENCH of TEST_MUX4 is
  ...
  signal SEL:
         STD_LOGIC_VECTOR(1 downto 0);
  signal A, B, C, D, F: STD_LOGIC;
begin
  ...
  M: MUX4 port map(SEL, A, B, C, D, F);
end BENCH;

Main test bench

architecture BENCH of TEST_MUX4 is
  ...
begin
  SEL <= "00", "01" after 30 NS,
  "10" after 60 NS, "11" after 90 NS,
  "XX" after 120 NS, "00" after 130 NS;
  A <= 'X',
       '0' after 10 NS,
       '1' after 20 NS;
  B <= 'X',
       '0' after 40 NS,
       '1' after 50 NS;
  C <= 'X',
       '0' after 70 NS,
       '1' after 80 NS;
  D <= 'X',
      '0' after 100 NS,
      '1' after 110 NS;
  ...
end BENCH;

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial.   Any content copied from the tutorial has been reproduced with permission.  http://www.doulos.com.