DE0-Nano

This blog contains a number of post aimed at learning VHDL and the Nios II processor. They are written to work with the DE0-Nano development board as the target platform.

Photo from: http://www.terasic.com.tw/en/

General

• Getting your design to load from the EPCS16 on the DE0-Nano development board - This post shows you how to get your design into the EPCS flash on the DE0-Nano Board.

• Scripting the process of programming the EPCS on the DE0-Nano - This post show how to develop a script that can be used to simplify the process of programming the EPCS on the DE0-Nano.

• Executing code on the Nios II directly after it has configured from the EPCS - This post show how to get code to execute from On-Chip RAM directly after configuration.

Getting a Nios II system running

• Simple Nios II on the DE0-Nano - Part 1 of 4 (Project creation) - This post takes you through the process of creating your first project ready to build a Nios II system.

• Simple Nios II on the DE0-Nano - Part 2 of 4 (Qsys) - This post uses Qsys to develop a basic Nios II system.

• Simple Nios II on the DE0-Nano - Part 3 of 4 (VHDL) - This post looks at how to write the VHDL to place your Nios II sytem in an FPGA.

• Simple Nios II on the DE0-Nano - Part 4 of 4 (Nios Software) - This post look at getting you first software application running on the Nios.

• Connecting the SDRAM to a Nios II on the DE0-Nano - This post looks at adding external SRAM to the Nios Processor.

• Using a PLL to correct the SDRAM clock when using a Nios II on the DE0-Nano - This post look at making the SDRAM access safer using a PLL.

• Reseting my Nios II - This post is a look at how to reset not only a Nios II processor but an FPGA in general.

Interesting Videos

• DE0-Nano FPGA VGA