VHDL STD_LOGIC

signal B: STD_LOGIC;
...
B <= '0';
...
B <= '1';
...
B <= 'X';


signal V: STD_LOGIC_VECTOR(7 downto 0);

v <="1010xxxx";
v(7) <= v(6);
v(1) <='1';
W <= v(5 downto 3); -- Slice
v(5 downto 3) <="10xz"

---

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity MUX4 is
 port (
   SEL:in STD_LOGIC_VECTOR(1 downto 0);
   A, B, C, D: in STD_LOGIC;
   F: out STD_LOGIC);
end MUX4;

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial.   Any content copied from the tutorial has been reproduced with permission.  http://www.doulos.com.