VHDL Design Entity Referance

G1: entity WORK.INV(ARCH)
  port map (SEL, SELB);
G2: entity WORK.AOI(V2)
  port map (SEL, A, SELB, B, F);

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial.   Any content copied from the tutorial has been reproduced with permission.  http://www.doulos.com.