VHDL Component Declaration and Instantiation

architecture STRUCTURE of MUX2 is
  component INV
    port (A: in  STD_LOGIC;
          F: out STD_LOGIC);
  end component;
  component AOI
    port (A, B, C, D: in STD_LOGIC;
          F: out STD_LOGIC);
  end component;
  signal SELB: STD_LOGIC;
begin
  G1: INV port map(SEL, SELB);
  G2: AOI port map(SEL, A, SELB, B, F);
end STRUCTURE;

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial.   Any content copied from the tutorial has been reproduced with permission.  http://www.doulos.com.