VHDL Concurrent Signal Assignmants

architecture RTL of ENT is
  signal A1, A2, XX: STD_LOGIC;
begin
   A1 <= A and B after 2 NS;
   A2 <= X1 and X2 after 2 NS;
   XX <= A1 or A2 after 2NS
end RTL;

An event or change in value will trigger a concurrent signal assignment.  There is a delay (propagation delay) of 2 NS from an event to the signal changing.

It does not matter what order the signals are written.

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial.   Any content copied from the tutorial has been reproduced with permission.  http://www.doulos.com.