VHDL Technology Dependent Components

architecture A1 of Block1 is
  ...
  component GlobalResetBuffer
    port (Pin: in Std_logic);
  end component;

  signal Reset: Std_logic;
begin

  G: GlobalResetBuffer
                    port map (Reset);

  process (Clock, Reset)
  begin
    if Reset = '0' then
      Q <= '0';
    elsif RISING_EDGE(Clock) then
      Q <= Data;
    end if;
  end process;
  ...


Sometime we need to use specific areas of the FPGA. We can do this in VHDL for example we have specified a global reset above. However the VHDL will no longer be vendor independent.

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial.   Any content copied from the tutorial has been reproduced with permission.  http://www.doulos.com.