VHDL Asynchronous FF Reset

process (Clock, Reset)
begin

  if Reset = '0' then
    Count <= "00000000";

  elsif RISING_EDGE(Clock) then

    if Load = '1' then
      Count <= Data;
    else
      Count <= Count + '1';
    end if;

  end if;

end process;


This example show a flip flop with asynchronous reset.

---


...
signal Count :
          STD_LOGIC_VECTOR(7 downto 0);
begin
  process (Clock, Reset)
  begin
    if Reset = '0' then
      Count <= "00000000";
    elsif RISING_EDGE(Clock) then
      if Load = '1' then
        Count <= Data;  --load the counter 
      else
        Count <= Count + '1'; -- increment the counter
      end if;
    end if;
  end process;

Asynchronous and Synchronous parts of a eight bit counter with synchronous load.

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial.   Any content copied from the tutorial has been reproduced with permission.  http://www.doulos.com.