Flip Flop with Enable

process (Clock)
begin
  if RISING_EDGE(Clock) then

    if Reset = '1' then
      Q <= '0';

    elsif Enable = '1' then
      Q <= Data;
    end if;

  end if;
end process;

Depending on the technology the enable will either make use of the specific feature of an FPGA or will be implemented using a multiplexer.

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial.   Any content copied from the tutorial has been reproduced with permission.  http://www.doulos.com.