VHDL Logical Operators

AND
OR
NOT
NAND
NOR
XOR
XNOR


y <= a AND b;

The STD_LOGIC will synthesize to a single wire.



type STD_ULOGIC is (
        'U', -- Value at time 0
        'X',  - Strong  - Unknown
        '0', - Strong 
        '1',   - Strong         'Z', -- High impedance
        'W', - Week, Pull up resistor. - Unknown
        'L',  - Week, Pull up resistor.        'H',  - Week, Pull up resistor.

        '-'); -- Don't care

case IP is
when "00" =>
  OP <= "0--1"; -- don't care
when "01" =>
  OP <= "1-0-";
when "10" =>
  OP <= "--10";
when others =>
  OP <= "101-";
end case;


---


type Opcode is (Add, Neg, Load,
                Store, Jmp, Halt);

signal S: Opcode := Halt;

variable
  V: Std_logic_vector(0 to 1) := "00";

initialize signals and variables using :=
Do not use initial values of synthesis. They are only used for simulation. 

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial.   Any content copied from the tutorial has been reproduced with permission.  http://www.doulos.com.