VHDL Enumeration Types

type Opcode is (Add, Neg, Load,

                Store, Jmp, Halt);

signal S: Opcode;

The names Add, Neg, Load, Store, Jmp, Halt do not represent any binary bit patterns.

---

architecture V1 of Ent is

  type Opcode is (Add, Neg, Load,

                  Store, Jmp, Halt);

  signal S: Opcode;

begin

  C1: Reg port map (..., S, ...);

  C2: Ctl port map (..., S, ...);

end;

The values will be encoded as a binary number 000,001,010,011 etc.

---

type BOOLEAN is (FALSE, TRUE); -- package standard

type BIT is ('0', '1'); -- package standard

type STD_ULOGIC is --- package standard logic

  ('U', 'X', '0', '1',

   'Z', 'W', 'L', 'H', '-');

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial.   Any content copied from the tutorial has been reproduced with permission.  http://www.doulos.com.