VHDL For Loop

for I in 0 to 3 loop
  F(I) <= A(I) and B(3-I);
  V := V xor A(I);
end loop;

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for I in 3 downto 0 loop
  F(I) <= A(I) and B(3-I); -- discrete gates
  V := V xor A(I); -- chain of xor gates
end loop;

The for loop will make multiple copies of the statements in side the loop.

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process (A, B)
  variable I: Std_logic;
begin
  for I in 0 to 3 loop
    F(I) <= A(I) and B(3-I);
    V := V xor A(I);
  end loop;

  I := not I;
end process;

The variable I is not the same I that is inside the loop. The I is hidden inside the loop. 

Rule: The for loop will only synthesis if its bounds are constant.

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial.   Any content copied from the tutorial has been reproduced with permission.  http://www.doulos.com.