Tuesday, 4 September 2012

VHDL While, Loop, Exit, Next

While Cond Loop

   Exit;

  Exit When Cond;

End Loop;

---

Loop
????
End Loop;

The While loop and the loop can not be synthesized. However they can be used to create test benches. We can exit a loop using the Exit or Exit when statements.

---


L1: for I in 0 to 7 loop
  L2: for J in 0 to 7 loop

    C := C + 1;

    exit L2 when A(J) = B(I);
    exit L1 when B(C) = 'U';
  end loop L2;
end loop L1;

We can add labels to loops. We can use the labels to exit the loops i.e L1 and L2.

---

Main: for I in 0 to 15 loop
    next Main when Reset = '0';
     ???
      ???
end loop Main;


The next statement causes the next iteration of the loop to execute.



Reference

This blog post contains notes taken when working through the Doulos Pacemaker tutorial.   Any content copied from the tutorial has been reproduced with permission.  http://www.doulos.com.

No comments:

Post a Comment