VHDL Case Statment

case SEL is
when "00" =>
  F <= A;
when "01" =>
  F <= B;
when "10" =>
  F <= C;
when "11" =>
  F <= D;
when others =>
  F <= 'X';
end case;

Rule 1: very possible combination of the case expression should be covered by a when statement. The OTHERS branch will catch any not covered.

Rule 2: Every possible case should only be covered once.

The case statement will be synthesis to a multiplexer. A latch will be create if all combinations of the signal are not catered for. 

case ADDRESS is

when 16 | 20 | 24 | 28 =>

  A <= '1';

  B <= '1';

when others =>

end case;

You can check for multiple cases using multiple assignments using the | symbol. any number of signals can be in the branch of a case statement.

case ADDRESS is

when 0 to 7 =>

  A <= '1';

when 8 to 15 =>

  B <= '1';

when 16 | 20 | 24 | 28 =>

  A <= '1';

  B <= '1';

when others =>

end case;

We can use ranges for the branches of a case statement.

A <= '0';

B <= '0';

case ADDRESS is

when 0 to 7 =>

  A <= '1';

when 8 to 15 =>

  B <= '1';

when 16 | 20 | 24 | 28 =>

  A <= '1';

  B <= '1';

when others =>

  null;

end case;

We can use null to show we did not want to do anything in that branch of the code.


Using a case to decode a small number of inputs is often better that an if because it will result in a better synthesis of logic on an FPGA.

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial.   Any content copied from the tutorial has been reproduced with permission.  http://www.doulos.com.