VHDL Incomplete Assignments

Rule 3: For combinational logic no incomplete assignments i.e. when an if statement does not assign a value to a signal for every possible combination. This will create a latch.



process (Enable, Data)
begin
  if Enable = '1' then
    Q <= Data;
  end if;
end process;

Incomplete assignments are when not all combinations of an if statement assign a value. the code above will synthesize to a transparent latch.

Reference

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This blog post contains notes taken when working through the Doulos Pacemaker tutorial.   Any content copied from the tutorial has been reproduced with permission.  http://www.doulos.com.