VHDL Variables

Variables could be synthesized as a wire or a register depending on how they are used.

-- Assume A = '0', B = '0', C = '1'

process (A, B, C)
  variable V: Std_logic;
begin
  V := A nand B;
  V := V nor C;
  F <= not V;
end process;

:= is the assignment of a variable. Unlike a signal (<=) the value of the variable changes immediately. Signal assignments are allays delayed i.e. the next run of the process. In the above example V is synthersised as two wires i.e V := (A nand B) nor C.

Variables can only be used within the process it is defined.

• If you assign a wire before using it it will become a wire.
• If you read a variable for assigning it it will become a FF.

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial.   Any content copied from the tutorial has been reproduced with permission.  http://www.doulos.com.