VHDL Signal Assignment

Rule 1: All inputs must be in the sensitivity list.
Rule 2: Outputs must only depend on current input values i.e. no feedback.
Rule 3: For combinational logic no incomplete assignments i.e. when an if statement does not assign a value to a signal for every possible combination. This will create a latch.

process (A, B, S, T)
begin
  S <= A nand B;
  T <= not S;
  F <= T;
end process;

The sensitivity list will cause the VHDL to execute on an event. 

• If A changes an event on S is created. However the value of S has not changed. There will be no event on either T or F.
• The event S will now cause the process to execute again.
• This process continues.

B<= a after 5ns;

The after does not create any delay on execution the process.

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial.   Any content copied from the tutorial has been reproduced with permission.  http://www.doulos.com.