VHDL Process

architecture V3 of AOI is
  signal AB, CD, O: STD_LOGIC;
begin
  process (A, B, C, D)
  begin
    AB <= A and B after 2 NS;
    CD <= C and D after 2 NS;
  end process;

  process (AB, CD)
  begin
    O <= AB or CD after 2 NS;
  end process;

  process (O)
  begin
    F <= not O after 1 NS;
  end process;
end V2;

You can give a process a label



P1: process (SEL, A, B, C)
begin
  if SEL = '1' then
    OP <= A and MASK;
  else
    OP <= B;
  end if;
end process;

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial.   Any content copied from the tutorial has been reproduced with permission.  http://www.doulos.com.