architecture RTL of ENT isAn event or change in value will trigger a concurrent signal assignment. There is a delay (propagation delay) of 2 NS from an event to the signal changing.
signal A1, A2, XX: STD_LOGIC;
begin
A1 <= A and B after 2 NS;
A2 <= X1 and X2 after 2 NS;
XX <= A1 or A2 after 2NS
end RTL;
It does not matter what order the signals are written.
Reference
This blog post contains notes taken when working through the Doulos Pacemaker tutorial. Any content copied from the tutorial has been reproduced with permission. http://www.doulos.com.
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