VHDL Design Entity

library ieee;
use ieee.std_logic_1164.all;

entity ent is
  port(a,b :in std_logic;
       z :out std_logic_vector(3 downto 0));
end ent;

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial.   Any content copied from the tutorial has been reproduced with permission.  http://www.doulos.com.