Up Down counter in VHDL

I have just posted a reply to the altera forum. The thread ask the question how would you design an up/down counter in VHDL. The follwing is my solution:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity people_count is
generic 
     (
  COUNTER_WIDTH: integer := 8
     );
port (
in_clk      : in std_logic;
in_reset    : in std_logic;
in_incCount : in std_logic;
in_decCount : in std_logic;

out_count : out std_logic_vector(COUNTER_WIDTH-1 downto 0)
);
end entity people_count;

architecture arch_people_count of people_count is

signal count: unsigned(COUNTER_WIDTH-1 downto 0);
signal count_up: std_logic;
signal count_down: std_logic;
begin
   
  count_up <= '1' when in_incCount ='1' and in_decCount = '0' else '0';
  count_down <= '1' when in_incCount ='0' and in_decCount = '1' else '0';
  
  process(in_clk, in_reset)
  begin
    if in_reset = '1' then
  count <= (others => '0');
    elsif rising_edge(in_clk) then 
  if (count_up = '1') then
        count <= count + 1;
elsif (count_down = '1') then
 count <= count - 1;
end if;
    end if;
  end process;
  
  out_count <= std_logic_vector(count);
  
end architecture arch_people_count;

happy counting :-)