How would you implement the following truth table straight in VHDL?
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
Example 1: you could use a with select statment as shown below:
library ieee;
use ieee.std_logic_1164.all;
entity truthtable is
port(in_a: in std_logic;
in_b: in std_logic;
in_c: in std_logic;
out_f: out std_logic);
end entity truthtable;
architecture arch_truthtable of truthtable is
begin
with std_logic_vector'(in_a,in_b,in_c) select
out_f <= std_logic'('0') when ("000"),
std_logic'('1') when ("001"),
std_logic'('1') when ("010"),
std_logic'('1') when ("011"),
std_logic'('1') when ("100"),
std_logic'('0') when ("101"),
std_logic'('0') when ("110"),
std_logic'('1') when ("111");
end architecture;This VHDL will produce the follwoing RTL model:
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