Test bench for a truth table

The following VHDL builds on For Loop for driving a testbench and is used to create a test bench for the VHDL truth_table defined here. 


library ieee;
use ieee.std_logic_1164.all;

entity testxx is
end entity;

architecture arch of testxx is

--The function to_string was taken from 
--http://www-ee.uta.edu/Online/Zhu/spring_2007/tutorial/how_to_print_objexts.txt
  function to_string(sv: Std_Logic_Vector) return string is
    use Std.TextIO.all;
    variable bv: bit_vector(sv'range) := to_bitvector(sv);
    variable lp: line;
  begin
    write(lp, bv);
    return lp.all;
  end;
  
  component truthtable is
   port(in_a:  in std_logic;
        in_b:  in std_logic;
     in_c:  in std_logic;
     out_f: out std_logic);
   end component;

  type tvector is array (7 downto 0) 
              of std_logic_vector(3 downto 0);

  constant test_vectors: tvector := ("0000", 
                                     "0011", 
                                    -- "0101", -- This is correct
                                     "0100",   -- This is an error
                                     "0111", 
                                     "1001", 
                                     "1010", 
                                     "1100",
                                     "1111");

  signal a,b,c,z_expected: std_logic;
  signal z : std_logic;
  signal test: std_logic_vector(3 downto 0); 
  
  begin
  
  table1:truthtable port map(in_a => a, in_b => b, in_c => c, out_f => z);
    
  process
    begin
       for i in 7 downto 0 loop
         test <= test_vectors(i);
        
        a <= test_vectors(i)(3);
        b <= test_vectors(i)(2);
        c <= test_vectors(i)(1);
        z_expected <= test_vectors(i)(0);
        
        wait for 10 ns;
        
        if (z = not z_expected) then
         report "vector=" & to_string(test);
         report "z_expected = " & Std_Logic'image(z_expected) & " z = " & Std_Logic'image(z);         
       end if;
       
       end loop;
      wait;
  end process;
  
end architecture;

Notice I have introduced an error when defining the constants which produces an output in modelsim as follows:

# ** Note: vector=0100
#    Time: 30 ns  Iteration: 0  Instance: /testxx
# ** Note: z_expected = '0' z = '1'
#    Time: 30 ns  Iteration: 0  Instance: /testxx