VHDL Test Bench Clock

ClockGenerator_1: process
begin
  for I in 1 to 1000 loop
    Clock <= '0';
    wait for 5 NS; 
    Clock <= '1';
    wait for 10 NS;
  end loop;
  wait; -- Remove this wait to loop for ever.
end process ClockGenerator_1;

The above example create 1000 clock pulses for a text bench. Frequency of clock is 1/(5ns+5ns).

---


ClockGenerator_2: process
begin
  while NOW < 15 US loop
    Clock <= '0';
    wait for 5 NS;
    Clock <= '1';
    wait for 10 NS;
  end loop;
  wait; -- Remove this wait to loop for ever.
end process ClockGenerator_2; 

The now is the current simulator time. The above example will create a clock for 15uS.

---


ClockGenerator_3: process
begin
  loop
    Clock <= '0';
    wait for 5 NS;
    Clock <= '1';
    wait for 10 NS;
    exit when NOW >= 15 US;
  end loop;
  wait;
end process ClockGenerator_3; 


Exit the loop when the stop time has been reached i.e NOW >= 15 US;

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial.   Any content copied from the tutorial has been reproduced with permission.  http://www.doulos.com.