VHDL State Encoding

type StateType is
         (Idle, Start, Stop, Clear);
signal State: StateType;


The states will be encoded as below. We can change the encoding by changing the order in the type statement.
Idle = 00
Start = 01
Stop = 01
Clear = 11

However some synthesis tools can be told to optimize the SM automatically. Do not turn on this option if you want to be in full control.

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Unreachable states are created with the following type def.


type StateType is
         (One, Two, Three, Four, Five);

This is ok but if you want to specify what happens specify the dummy states you can create this as follows:

type StateType is
         (One, Two, Three, Four, Five,
          Dummy1, Dummy2, Dummy3);

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial.   Any content copied from the tutorial has been reproduced with permission.  http://www.doulos.com.