VHDL SM Separating Registers

architecture RegistersPlusLogic of FSM is
  type StateType is (Idle, Start, Stop, Clear);
  signal State: StateType;
begin
  Registers: process
  begin
    wait until RISING_EDGE(Clock);
    if Reset = '0' then
      State <= Idle;
    else
      State <= NextState;
    end if;
  end process;

  C_logic: process (State)
  begin
    if    State = Clear then NextState <= Idle;
                             F <= '1';
    elsif State = Idle  then NextState <= Start;
                             G <= '1';
    elsif State = Start then NextState <= Stop;
    else                     NextState <= Clear;
    end if;

  end process;
end;

Reference

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This blog post contains notes taken when working through the Doulos Pacemaker tutorial.   Any content copied from the tutorial has been reproduced with permission.  http://www.doulos.com.