VHDL The Five Process Styles

Style 1: Pure combinational logic


T1: process (All_Inputs)
begin
  ... Pure combinational logic
end process;

• Rule: Complete sensitivity list 
• Rule: All outputs completely assigned
• Rule: No feedback.

---
Style 2: Transparent Latch


T2: process (All_Inputs)
begin
  if Enable = '1' then
    ... Transparent latches + logic
  end if;
end process;

The transparent latch has:

• Rule: a single if statement with not else.
• Rule: Complete sensitivity list 
• Rule: No feedback.

---
Style 3: FF Using IF 


T3: process (Clock)
begin
  if RISING_EDGE(Clock) then
     ... Flipflops + logic
  end if;
end process;

• Rule: The assignments must be syncronised to the clock edge
• Rule: The must not be an ELSE statement
• Rule: Check tool support of  RISING_EDGE
• Rule: No statements must be placed after the END IF

--
Style 4: FF Using Wait


T4: process
begin
  wait until RISING_EDGE(Clock);
  ... Flipflops + logic
end process;

• Rule: The assignments must be syncronised to the clock edge
• Rule: Check tool support of  RISING_EDGE

--
Style 5: FF with Asynchronous Inputs


T5: process (Clock, Reset)
begin
  if Reset = '0' then
    ... Asynchronous actions
  elsif RISING_EDGE(Clock) then
    ... Flipflops + logic
  end if;
end process;

• Rule: All asynchronous inputs must me added to the sensitivity list
• Rule: You must check their value first before the clock check.
• Rule: The assignments must be  syncronised to the clock edge
• Rule: The must not be an ELSE statement
• Rule: Check tool support of  RISING_EDGE
• Rule: No statements must be placed after the END IF

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial.   Any content copied from the tutorial has been reproduced with permission.  http://www.doulos.com.