VHDL Edge Triggered Flip Flop

process (Clock)
begin

  if Clock'EVENT and Clock = '1' then

    Q0 <= D0;
    Q1 <= D1;

  end if;

end process;


The tick event attribute is used to create a latch controlled by a clock. The Clock'EVENT will infer a flip flop.

We could use a function in the 1164 packge to look at clock edges.


library IEEE;
use IEEE.STD_LOGIC_1164.all;

...

process (Clock)
begin

  if RISING_EDGE(Clock) then
    Q <= D;
  end if;

end process;

---

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial.   Any content copied from the tutorial has been reproduced with permission.  http://www.doulos.com.