Synthesis if Arithmetic Operators

F <= A + B;

This will synthesis to either:
1 - Non-optimal connection of FPGA cells or
2- Optimized structure of FPGA cells.

Some thisis acn take a + or - and map it directly to a standard block. But sometimes we need to use a vendor specific component our self's:

C1: ADDER8 port map (A,B,F)

The implementation depends on speed or size needed i.e. ripple carry adder v carry look-ahead adder.

Resource sharing can happen if the operators are on different paths of the same if statement.


process (A, B, C, D, K)
begin
  if K then
    Z <= A + B; -- 8 Bit
  else
    Z <= C + D;
  end if;
end process;


Share the same adder block.

However if the synthesis tool does not support resource sharing then the code could be rewritten to force the resource to be shared.


process (A, B, C, D, K)
  variable V1, V2 : ...
begin
  if K then
    V1 := A;
    V2 := B;
  else
    V1 := C;
    V2 := D;
  end if;
  Z <= V1 + V2;

end process;

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial.   Any content copied from the tutorial has been reproduced with permission.  http://www.doulos.com.