VHDL Equivalent Concurrent Statments

architecture V2 of AOI is
  signal AB, CD, O: STD_LOGIC;
begin
  AB <= A and B after 2 NS;
  CD <= C and D after 2 NS;
  O <= AB or CD after 2 NS;
  F <= not O after 1 NS;
end V2;

Each of the concurrent statments are processes in their own right.

----

L: F <= A when S0 = '1' else

        B when S1 = '1' else

        C;

The above is equivalent to an if statement inside a process.

Reference

http://www.doulos.com

This blog post contains notes taken when working through the Doulos Pacemaker tutorial.   Any content copied from the tutorial has been reproduced with permission.  http://www.doulos.com.