For Loop for driving a testbench

Building again on my blog post Reporting on Std_Logic_Vector I wanted to build on the VHDL to split the constant out into a number of signal that I could use as part of a test bench. Before I look at how the test bench could be constructed the following VHDL will split out the signals a,b,c and z_expected: 


library ieee;
use ieee.std_logic_1164.all;

entity testxx is
end entity;

architecture arch of testxx is

--The function to_string was taken from 
--http://www-ee.uta.edu/Online/Zhu/spring_2007/tutorial/how_to_print_objexts.txt
  function to_string(sv: Std_Logic_Vector) return string is
    use Std.TextIO.all;
    variable bv: bit_vector(sv'range) := to_bitvector(sv);
    variable lp: line;
  begin
    write(lp, bv);
    return lp.all;
  end;
  
  type tvector is array (7 downto 0) 
              of std_logic_vector(3 downto 0);

  constant test_vectors: tvector := ("0000", 
                                     "0011", 
                                     "0101", 
                                     "0111", 
                                     "1001", 
                                     "1010", 
                                     "1100",
                                     "1111");

  signal a,b,c,z_expected: std_logic;
  
  begin
  
  process
    begin
       for i in 7 downto 0 loop
        report "loop_i=" & integer'image(i);
        report "length=" 
               & integer'image(test_vectors(i)'length);
        report "vector=" & to_string(test_vectors(i));
        
        a <= test_vectors(i)(3);
        b <= test_vectors(i)(2);
        c <= test_vectors(i)(1);
        z_expected <= test_vectors(i)(0);
        
        wait for 10 ns;
       end loop;
      wait;
  end process;
  
  process(a)
    begin 
      report "----a has changed to: " & Std_Logic'image(a);
  end process;
  
  process(b)
    begin 
      report "----b has changed to: " & Std_Logic'image(b);
  end process;
  
  process(c)
    begin 
      report "----c has changed to: " & Std_Logic'image(c);
  end process;
  
  process(z_expected)
    begin 
      report "----z_expected has changed to: " & Std_Logic'image(z_expected);
  end process;
end architecture;

The output from modelsim is a follows:


Note: ----z_expected has changed to: 'U'
#    Time: 0 ps  Iteration: 0  Instance: /testxx
# ** Note: ----c has changed to: 'U'
#    Time: 0 ps  Iteration: 0  Instance: /testxx
# ** Note: ----b has changed to: 'U'
#    Time: 0 ps  Iteration: 0  Instance: /testxx
# ** Note: ----a has changed to: 'U'
#    Time: 0 ps  Iteration: 0  Instance: /testxx
# ** Note: loop_i=7
#    Time: 0 ps  Iteration: 0  Instance: /testxx
# ** Note: length=4
#    Time: 0 ps  Iteration: 0  Instance: /testxx
# ** Note: vector=0000
#    Time: 0 ps  Iteration: 0  Instance: /testxx
# ** Note: ----a has changed to: '0'
#    Time: 0 ps  Iteration: 1  Instance: /testxx
# ** Note: ----b has changed to: '0'
#    Time: 0 ps  Iteration: 1  Instance: /testxx
# ** Note: ----c has changed to: '0'
#    Time: 0 ps  Iteration: 1  Instance: /testxx
# ** Note: ----z_expected has changed to: '0'
#    Time: 0 ps  Iteration: 1  Instance: /testxx
# ** Note: loop_i=6
#    Time: 10 ns  Iteration: 0  Instance: /testxx
# ** Note: length=4
#    Time: 10 ns  Iteration: 0  Instance: /testxx
# ** Note: vector=0011
#    Time: 10 ns  Iteration: 0  Instance: /testxx
# ** Note: ----c has changed to: '1'
#    Time: 10 ns  Iteration: 1  Instance: /testxx
# ** Note: ----z_expected has changed to: '1'
#    Time: 10 ns  Iteration: 1  Instance: /testxx
# ** Note: loop_i=5
#    Time: 20 ns  Iteration: 0  Instance: /testxx
# ** Note: length=4
#    Time: 20 ns  Iteration: 0  Instance: /testxx
# ** Note: vector=0101
#    Time: 20 ns  Iteration: 0  Instance: /testxx
# ** Note: ----b has changed to: '1'
#    Time: 20 ns  Iteration: 1  Instance: /testxx
# ** Note: ----c has changed to: '0'
#    Time: 20 ns  Iteration: 1  Instance: /testxx
# ** Note: loop_i=4
#    Time: 30 ns  Iteration: 0  Instance: /testxx
# ** Note: length=4
#    Time: 30 ns  Iteration: 0  Instance: /testxx
# ** Note: vector=0111
#    Time: 30 ns  Iteration: 0  Instance: /testxx
# ** Note: ----c has changed to: '1'
#    Time: 30 ns  Iteration: 1  Instance: /testxx
# ** Note: loop_i=3
#    Time: 40 ns  Iteration: 0  Instance: /testxx
# ** Note: length=4
#    Time: 40 ns  Iteration: 0  Instance: /testxx
# ** Note: vector=1001
#    Time: 40 ns  Iteration: 0  Instance: /testxx
# ** Note: ----a has changed to: '1'
#    Time: 40 ns  Iteration: 1  Instance: /testxx
# ** Note: ----b has changed to: '0'
#    Time: 40 ns  Iteration: 1  Instance: /testxx
# ** Note: ----c has changed to: '0'
#    Time: 40 ns  Iteration: 1  Instance: /testxx
# ** Note: loop_i=2
#    Time: 50 ns  Iteration: 0  Instance: /testxx
# ** Note: length=4
#    Time: 50 ns  Iteration: 0  Instance: /testxx
# ** Note: vector=1010
#    Time: 50 ns  Iteration: 0  Instance: /testxx
# ** Note: ----c has changed to: '1'
#    Time: 50 ns  Iteration: 1  Instance: /testxx
# ** Note: ----z_expected has changed to: '0'
#    Time: 50 ns  Iteration: 1  Instance: /testxx
# ** Note: loop_i=1
#    Time: 60 ns  Iteration: 0  Instance: /testxx
# ** Note: length=4
#    Time: 60 ns  Iteration: 0  Instance: /testxx
# ** Note: vector=1100
#    Time: 60 ns  Iteration: 0  Instance: /testxx
# ** Note: ----b has changed to: '1'
#    Time: 60 ns  Iteration: 1  Instance: /testxx
# ** Note: ----c has changed to: '0'
#    Time: 60 ns  Iteration: 1  Instance: /testxx
# ** Note: loop_i=0
#    Time: 70 ns  Iteration: 0  Instance: /testxx
# ** Note: length=4
#    Time: 70 ns  Iteration: 0  Instance: /testxx
# ** Note: vector=1111
#    Time: 70 ns  Iteration: 0  Instance: /testxx
# ** Note: ----c has changed to: '1'
#    Time: 70 ns  Iteration: 1  Instance: /testxx
# ** Note: ----z_expected has changed to: '1'
#    Time: 70 ns  Iteration: 1  Instance: /testxx

Reporting on Std_Logic_Vector

In my blog post VHDL Reporting an integer I developed some VHDL to print out a list of number from index of a FOR LOOP. The following VHDL expands this idea and looks at how to print out a number of Std_Logic_Vectors defined in as a constant.


library ieee;
use ieee.std_logic_1164.all;

entity testxx is
end entity;

architecture arch of testxx is

--The function to_string was taken from 
--http://www-ee.uta.edu/Online/Zhu/spring_2007/tutorial/how_to_print_objexts.txt
  function to_string(sv: Std_Logic_Vector) return string is
    use Std.TextIO.all;
    variable bv: bit_vector(sv'range) := to_bitvector(sv);
    variable lp: line;
  begin
    write(lp, bv);
    return lp.all;
  end;
  
  type tvector is array (7 downto 0) 
              of std_logic_vector(3 downto 0);

  constant test_vectors: tvector := ("0000", 
                                     "0011", 
                                     "0101", 
                                     "0111", 
                                     "1001", 
                                     "1010", 
                                     "1100",
                                     "1111");

  begin
  
  process
    begin
       for i in 7 downto 0 loop
        report "loop_i=" & integer'image(i);
        report "length=" 
               & integer'image(test_vectors(i)'length);
        report "vector=" & to_string(test_vectors(i));
        wait for 10 ns;
       end loop;
      wait;
  end process;
    
end architecture;

The output from modelsim is as follows:


# ** Note: loop_i=7
#    Time: 0 ps  Iteration: 0  Instance: /testxx
# ** Note: length=4
#    Time: 0 ps  Iteration: 0  Instance: /testxx
# ** Note: vector=0000
#    Time: 0 ps  Iteration: 0  Instance: /testxx
# ** Note: loop_i=6
#    Time: 10 ns  Iteration: 0  Instance: /testxx
# ** Note: length=4
#    Time: 10 ns  Iteration: 0  Instance: /testxx
# ** Note: vector=0011
#    Time: 10 ns  Iteration: 0  Instance: /testxx
# ** Note: loop_i=5
#    Time: 20 ns  Iteration: 0  Instance: /testxx
# ** Note: length=4
#    Time: 20 ns  Iteration: 0  Instance: /testxx
# ** Note: vector=0101
#    Time: 20 ns  Iteration: 0  Instance: /testxx
# ** Note: loop_i=4
#    Time: 30 ns  Iteration: 0  Instance: /testxx
# ** Note: length=4
#    Time: 30 ns  Iteration: 0  Instance: /testxx
# ** Note: vector=0111
#    Time: 30 ns  Iteration: 0  Instance: /testxx
# ** Note: loop_i=3
#    Time: 40 ns  Iteration: 0  Instance: /testxx
# ** Note: length=4
#    Time: 40 ns  Iteration: 0  Instance: /testxx
# ** Note: vector=1001
#    Time: 40 ns  Iteration: 0  Instance: /testxx
# ** Note: loop_i=2
#    Time: 50 ns  Iteration: 0  Instance: /testxx
# ** Note: length=4
#    Time: 50 ns  Iteration: 0  Instance: /testxx
# ** Note: vector=1010
#    Time: 50 ns  Iteration: 0  Instance: /testxx
# ** Note: loop_i=1
#    Time: 60 ns  Iteration: 0  Instance: /testxx
# ** Note: length=4
#    Time: 60 ns  Iteration: 0  Instance: /testxx
# ** Note: vector=1100
#    Time: 60 ns  Iteration: 0  Instance: /testxx
# ** Note: loop_i=0
#    Time: 70 ns  Iteration: 0  Instance: /testxx
# ** Note: length=4
#    Time: 70 ns  Iteration: 0  Instance: /testxx
# ** Note: vector=1111
#    Time: 70 ns  Iteration: 0  Instance: /testxx

VHDL Reporting an integer

I have been looking at test benches and learning about FOR LOOPS. I wanted to write some simple VHDL to print out some the numbers in the index of a for loop. This turned out to be more difficult than I first thought until I discovered how to convert an integer into a string using integer'image(i). The following code loops around 11 time and outputs the index from the loop:


entity testxx is
end entity;

architecture arch of testxx is
begin
  process
    begin
    for i in 0 to 10 loop
      report "julian=" & integer'image(i);
      wait for 10 ns;
     end loop;
     wait;
   end process;
end architecture;


The output from modelsim can be seen below:


run -all
# ** Note: julian=0
#    Time: 0 ps  Iteration: 0  Instance: /testxx
# ** Note: julian=1
#    Time: 10 ns  Iteration: 0  Instance: /testxx
# ** Note: julian=2
#    Time: 20 ns  Iteration: 0  Instance: /testxx
# ** Note: julian=3
#    Time: 30 ns  Iteration: 0  Instance: /testxx
# ** Note: julian=4
#    Time: 40 ns  Iteration: 0  Instance: /testxx
# ** Note: julian=5
#    Time: 50 ns  Iteration: 0  Instance: /testxx
# ** Note: julian=6
#    Time: 60 ns  Iteration: 0  Instance: /testxx
# ** Note: julian=7
#    Time: 70 ns  Iteration: 0  Instance: /testxx
# ** Note: julian=8
#    Time: 80 ns  Iteration: 0  Instance: /testxx
# ** Note: julian=9
#    Time: 90 ns  Iteration: 0  Instance: /testxx
# ** Note: julian=10
#    Time: 100 ns  Iteration: 0  Instance: /testxx

Truth Table in VHDL

Lots of people view this page. However I have no idea if its of any use. Please leave a comment to tell me if you found what you were looking for. Thanks - J

How would you implement the following truth table straight in VHDL?
0 0 0      0
0 0 1      1
0 1 0      1
0 1 1      1
1 0 0      1
1 0 1      0
1 1 0      0
1 1 1      1

Example 1: you could use a with select statment as shown below:

library ieee;
use ieee.std_logic_1164.all; 

entity truthtable is
port(in_a:  in std_logic;
     in_b:  in std_logic;
 in_c:  in std_logic;
 out_f: out std_logic);
end entity truthtable; 

architecture arch_truthtable of truthtable is
begin 

with std_logic_vector'(in_a,in_b,in_c) select
out_f <= std_logic'('0') when ("000"),
         std_logic'('1') when ("001"),
         std_logic'('1') when ("010"),
         std_logic'('1') when ("011"),
         std_logic'('1') when ("100"),
         std_logic'('0') when ("101"),
         std_logic'('0') when ("110"),
         std_logic'('1') when ("111"); 

end architecture;

This VHDL will produce the follwoing RTL model:

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Introduction to XML

XML Processor
An application used to access and process and XML document is known as an XML processor. XDocument is the name of the XML processor used in C#.

XML is a data object created from one or more files. It can have two kinds of structure associated with it a physical structure and a logical structure.

An XML processor must support UTF-8 and UTF-16.

Physical Structure
The physical structure of an XML document is a set of entities. There are two types of entities parsed and un-parsed.

The DTD can be use to check if the XML is valid and it can be used to store commonly used text.

We can also include binary entities such as images into an XML document. 

Parsed Entities
A parsed entity represents text that is parsed by an XML processor. It will always have at least one entity a document entity with no DTD. Parsed entities replace the text the entity.

Un-parsed entity
Un-parsed entity are used to include non XML data in an XML file. It must have an identity and a type.

Entity both parsed and un-paresd are added to the DTD document.

Logical structure
The logical structure of an XML file is an abstraction of the physical structure of the XML. This is the hierarchy of an XML document.